Xilinx V2.1 Manual de usuario descargar pdf (Pagina 105)

Memory 105

Xilinx Blocks

Xilinx LogiCORE

The block uses the Xilinx LogiCORE: Dual Port Block Memory v3.2 The address

width must be equal to

where d denotes the memory depth.

The tables below show the widths that are acceptable for each depth.

The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\blkmemdp_v3_2\do

c\dp_block_mem.pdf

Table: Maximum Width for Various Depth Ranges (Virtex/Virtex-E)

Depth Width

2 to 512 256

513 to 1024 256

1025 to 2048 256

2049 to 4096 192

4097 to 8192 96

8193 to 16K 48

16K+1 to 32K 24

32K+1 to 64K 12

64K+1 to 128K 6

128K+1 to 256K 3

Table: Maximum Width for Various Depth Ranges (Virtex-II)

Depth Width

2 to 512 256

513 to 1024 256

1025 to 2048 256

2049 to 4096 192

4097 to 8192 96

8193 to 16K 48

16K+1 to 32K 24

32K+1 to 64K 12

64K+1 to 128K 6

128K+1 to 256K 3

256K+1 to 512K 6

512K+1 to 1024K 3

log

1 2 ... 100 101 102 103 104 105 106 107 108 109 110 ... 147 148

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Xilinx V2.1 Manual de usuario Pagina 105