Xilinx V2.1 Manual de usuario

— Printed in U.S.A.Xilinx SystemGenerator v2.1forSimulinkUser GuideXilinx BlocksetReference GuideIntroductionXilinx Blockset OverviewXilinx BlocksSys

10 Xilinx Development SystemXilinx System Generator v2.1 Reference Guide3 and simply use floating point operations in hardware. The answer is that most

100 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe block parameters dialog box can be invoked by double-clicking the icon in

MATLAB I/O 101Xilinx BlocksNET "Dout<2>" FAST;NET "Dout_valid" FAST;• Specify IOB Location Constraints: Checking this optio

102 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideMemoryThis section contains Xilinx blocks that use Xilinx memory LogiCOREs.Du

Memory 103Xilinx Blocksby the port’s address input. During a write cycle, the user can configure the behaviorof the data out ports A/B to one of the fo

104 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideVirtex, Virtex-E and Spartan-II families support only Read After Write. Virte

Memory 105Xilinx BlocksXilinx LogiCOREThe block uses the Xilinx LogiCORE: Dual Port Block Memory v3.2 The addresswidth must be equal towhere d denotes

106 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideFIFOThe Xilinx FIFO block implements a First-In-First-Out memoryqueue.Values

Memory 107Xilinx Blocks• Store Only Valid Data: when checked, the block will not store any invaliddata words; i.e., when the din sample is invalid, th

108 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by

Memory 109Xilinx BlocksOther parameters usedby thisblock areexplained in the CommonParameters sectionof the previous chapter.Xilinx LogiCOREThe block

The System Generator Design Flow 11IntroductionThe System Generator design flow is shown in the following figure.Figure 1-1: System Generator design fl

110 Xilinx Development SystemXilinx System Generator v2.1 Reference Guidebetween 16 to 4096, inclusive for the other FPGA families. The word width mus

Memory 111Xilinx BlocksBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model.Fig

112 Xilinx Development SystemXilinx System Generator v2.1 Reference Guide• Read After Write• Read Before Write• No Read On WriteThe write modes can be

Memory 113Xilinx BlocksXilinx LogiCOREThe block always uses a Xilinx LogiCORE Single Port Block Memory V3.2 orDistributed Memory V5.0. For the block m

114 Xilinx Development SystemXilinx System Generator v2.1 Reference Guide%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\blkmemsp_v3_2\doc\sp_block_mem.

State Machine 115Xilinx Blocksstream of bits. The state transition diagram and equivalent transition table are shownbelow.Figure 3-77: Mealy State M

116 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe rows of the matrices correspond to the current state, and columns corresp

State Machine 117Xilinx BlocksA block diagram of this type of state machine is shown below:Figure 3-80: Moore State Machine block diagramThe block i

118 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe Next State Matrix and the and Output Array are composed in the following

State Machine 119Xilinx BlocksXilinx LogiCOREThis block uses Version 3.2 of the Xilinx Single Port Block Memory LogiCORE andVersion 5.0 of the Xilinx

12 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideSimulink hierarchy into a hierarchical VHDL netlist. In addition, System Gene

120 Xilinx Development SystemXilinx System Generator v2.1 Reference Guidestream of bits. The state transition diagram and equivalent transition table

State Machine 121Xilinx BlocksThe Registered Mealy State Machine block is configured with next state and outputmatrices obtained from the next state/ou

122 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe number of bits used to implement a registered mealy state machine is give

State Machine 123Xilinx BlocksRegistered Moore State MachineThe Xilinx Registered MooreState Machine blockimplementsa state machine whose output depen

124 Xilinx Development SystemXilinx System Generator v2.1 Reference Guidestream of bits. The state transition diagram and next state/output table are

State Machine 125Xilinx BlocksThe Next State Matrix and the Output Array are composed in the following way:Figure 3-90: Construction of Next State a

126 Xilinx Development SystemXilinx System Generator v2.1 Reference GuidewhereNs = total number of next state logic block RAM bitsk =ds= depth of stat

Using the System Generator installer 127System Generator Software FeaturesChapter 4System Generator Software FeaturesThis chapter briefly describes how

128 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideInstalled System Generator directoryThe installer will create the following d

Using Black Boxes 129System Generator Software FeaturesNote - For this example to run correctly, you must change your directory (cd withinthe MATLAB c

Hardware Handshaking 13IntroductionGenerator then propagates signal types and precisions as appropriate. Theautomatically chosen type is the least ex

130 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideUse of mixed language projectsSystem Generator v2.1 supports mixed language (

Use of mixed language projects 131System Generator Software Featuresenter information describing clocks, parameter names, types and values asappropria

132 Xilinx Development SystemXilinx System Generator v2.1 Reference Guidevlog<file>line for each Verilog wrapper that is listed in the verilogFi

Using the System Generator Constraints Files 133System Generator Software Featuresenable or clear port may result in large fanout signals, thus degrad

134 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe division of the design into parts, and the speed at which each part must

Using the System Generator Constraints Files 135System Generator Software FeaturesThe ce2_group contains the blocksoperating at twice the system perio

136 Xilinx Development SystemXilinx System Generator v2.1 Reference Guidecell array of strings in the box labeled IOB Pad Locations. Locations are pa

Files automatically created by System Generator 137System Generator Software FeaturesFiles automatically created by System GeneratorWhen aSystem Gener

138 Xilinx Development SystemXilinx System Generator v2.1 Reference Guide• sysgen.log - log file.• xlRunScripts.log - log file showing status of post-pr

Xilinx ISE 4.1i Project Navigator 139Using the Xilinx SoftwareChapter 5Using the Xilinx SoftwareThis chapter describes how to process your System Gene

14 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBit-True and Cycle-True ModelingSystem Generator produces a hardware implement

140 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideNavigator properties dialog. Right-click on the device and default package at

Xilinx ISE 4.1i Project Navigator 141Using the Xilinx SoftwareIn the Sources window, select the top-level VHDL module in your design. Now youwill not

142 Xilinx Development SystemXilinx System Generator v2.1 Reference Guide• pn_posttranslate.do - this file will run a simulation on the output of theXi

Using an EDIF software flow 143Using the Xilinx Softwarewere generated in Simulink. Provided that your design was error free, the ModelSimconsole wind

144 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideXilinx supplies two sets of instructions for compiling your IP libraries usin

Xilinx software tools resources 145Using the Xilinx SoftwareAfter you make this association, your System Generator projects within ProjectNavigator wi

146 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideChapter 6Auxiliary FilesDemonstration designsSeveral demonstration designs ha

Perl scripts 147Auxiliary FilesYou can also launch the MATLAB Demos window from the MATLAB console bytyping:>> demoPerl scriptsAs a convenience,

148 Xilinx Development SystemXilinx System Generator v2.1 Reference Guide

What is a Xilinx Block? 15Xilinx Blockset OverviewChapter 2Xilinx Blockset OverviewThis chapter gives an overview of the Xilinx Blockset, including ba

16 Xilinx Development SystemXilinx System Generator v2.1 Reference Guideportion of a Simulink model to be implemented in an FPGA must be built exclusi

The Nature of Signals in the Xilinx Blockset 17Xilinx Blockset OverviewAs an example, the figures shown below depict the Xilinx Negate block parameters

18 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideUse of Xilinx Smart-IP Cores by the System GeneratorTo increase hardware perfo

Common Options in Block Parameters Dialog Box 19Xilinx Blockset OverviewXilinx LogiCORE VersionsThe Xilinx LogiCORE blocks (indicating the version n

2 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideAbout This ManualThis document is a reference guide for system designers who ar

20 Xilinx Development SystemXilinx System Generator v2.1 Reference Guidespecific parameters are described in the specific block documentation in the nex

Common Options in Block Parameters Dialog Box 21Xilinx Blockset OverviewPrecisionThe fundamental computational mode in the Xilinx Blockset is arbitrar

22 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideIn the Simulink environment, the Override with Doubles option allows you tosim

Basic Elements 23Xilinx BlocksChapter 3Xilinx BlocksThis chapter describes each Xilinx block in detail. Xilinx blocks are grouped within sixcategories

24 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by d

Basic Elements 25Xilinx BlocksThe wrapper file is named to match the top level VHDL file generated for yourproject. For example, if your top level file i

26 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideAddressable Shift RegisterThe Xilinx Addressable Shift Register block is a var

Basic Elements 27Xilinx BlocksBlock Parameters Dialog BoxThe Addressable Shift Register Block Parameters Dialog Box can be invoked bydouble-clicking t

28 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlack BoxThe Xilinx Black Box token enables you to instantiate your ownspecial

Basic Elements 29Xilinx Blocksinfer them in the generated VHDL. The block parameters dialog box can be invokedby double-clicking the icon in your Simu

3Additional ResourcesFor additional information, go to http://support.xilinx.com. The followingtable lists some additional resources.Resource Descript

30 Xilinx Development SystemXilinx System Generator v2.1 Reference Guideinput and output ports respectively. To configure the black box, enter the para

Basic Elements 31Xilinx BlocksConstantThe Xilinx Constant block generates a constant.This block is similar to theSimulink constant block, but can be u

32 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by d

Basic Elements 33Xilinx BlocksThe block can be configured as a free running up or down counter byselecting the Provide Reset Pin option on the block pa

34 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe Counter block parameters dialog box is invoked

Basic Elements 35Xilinx BlocksXilinx LogiCOREThe block always uses the Xilinx LogiCORE: Binary Counter V5.0.The Core datasheet can be found on your lo

36 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideDown SampleThe Xilinx Down Sample block reduces the sample rate at the pointwh

Basic Elements 37Xilinx BlocksBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by double-clicking the icon in yourSimulink mo

38 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideMuxThe Xilinx Mux block implements a multiplexer.The block has one select inpu

Basic Elements 39Xilinx Blocks%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\doc\bus_mux.pdfParallel to SerialThe Parallel to Serial bloc

4 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideConventionsThis document uses the following conventions. An example illustrates

40 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxFigure 3-15: Parallel to Serial block parameters

Basic Elements 41Xilinx BlocksBlock InterfaceThe block has one input port for the data and an optional input reset port. The initialoutput value is sp

42 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideReinterpretThe Reinterpret block forces its output to a new type without anyre

Basic Elements 43Xilinx BlocksBlock Parameters Dialog boxFigure 3-17: Reinterpret block parameters dialog boxParameters specific to the block are:• F

44 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe following waveform illustrates the block’s behavior:Figure 3-18: Example

Basic Elements 45Xilinx Blocks• Binary Point: Output binary point locationOther parameters usedby thisblock areexplained in the CommonParameters secti

46 Xilinx Development SystemXilinx System Generator v2.1 Reference Guideonly the first three fractional bits. The following diagram illustrates how to

Basic Elements 47Xilinx BlocksFigure 3-22: Slice block parameters dialog box showing different optionsParameters specific to the block are:• Specify

48 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe following diagram illustrates the operation of this block.Figure 3-23: S

Basic Elements 49Xilinx BlocksIt is instructive to note that the following model produces behavior identical to theone with the Sync block. This one,

5ContentsChapter 1 IntroductionIndustry and Product Overview ...8System

50 Xilinx Development SystemXilinx System Generator v2.1 Reference Guideadded to the channel that is last to present a valid input sample. Note that i

Basic Elements 51Xilinx Blocksfrom din to dout. Whenever possible, put a register or delay block after an up sampleblock.Figure 3-28: Example of up

52 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideCommunicationThe blocks in the Communication library implement functions used

Communication 53Xilinx BlocksBlock Parameters Dialog BoxThe following figure shows the block parameters dialog box.Figure 3-31: Convolutional encoder

54 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideDepunctureThe Xilinx Depuncture block allows you to insert arbitrary symbol in

Communication 55Xilinx BlocksBlock Parameters Dialog BoxThe Xilinx depuncture block can be configured using its Block Parameters dialog box.Figure 3-33

56 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideFigure 3-34: Forney convolutional interleaver with a constant differencebetw

Communication 57Xilinx BlocksWhen the branch lengths are specified as an array, the block operates the same ineither interleaver or deinterleaver mode

58 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe Core datasheet can be found on your local disk at:%XILINX%\coregen\ip\xili

Communication 59Xilinx BlocksBlock Parameters Dialog BoxThe Xilinx puncture block can be configured using its Block Parameters dialog box.Figure 3-38:

6 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideConcat ...

60 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe probability of each of the three outcomes depends on the particular Reed-S

Communication 61Xilinx BlocksBlock Parameters Dialog BoxThe RS Decoder block can be configured using its Block Parameters dialog box.Figure 3-40: Ree

62 Xilinx Development SystemXilinx System Generator v2.1 Reference Guide♦ IESS-308 (208): implements IESS-308 specification (208, 192) shortened RScode

Communication 63Xilinx Blocks• Scaling Factor: Scaling factor for the generator polynomial root index.Normally h is 1; however, it can be any positive

64 Xilinx Development SystemXilinx System Generator v2.1 Reference Guidetype of errors that can be corrected depends on the characteristics of the Ree

Communication 65Xilinx BlocksBlock InterfaceThe Xilinx RS Encoder block has two inputs (din, rst) and three output (dout,info and rfd) ports. The RS E

66 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe RS Encoder block can be configured using its Blo

Communication 67Xilinx Blocks♦ IESS-308 (225): implements IESS-308 specification (225, 205) shortened RScode.• Symbol Width: specifies the symbol width

68 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideOther parameters used by this block aredescribed inthe CommonParameters sectio

Communication 69Xilinx BlocksBlock InterfaceThe Viterbi Decoder has eithertwo or threeinputports and one output port. The decoder can haveeither two o

7Gateway Out...99Quantization Error Blocks ...

70 Xilinx Development SystemXilinx System Generator v2.1 Reference Guide• Traceback Length:Length of the traceback throughthe Viterbi trellis.Optimall

DSP 71Xilinx BlocksBlock InterfaceThe CIC Block has one input and one output port. The input port can be between 1and 32 bits (inclusive).The twobasi

72 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe CIC Block can be configured using its Block Para

DSP 73Xilinx BlocksDDSThe Xilinx DDS Block implements a direct digital synthesizer (DDS),also commonly called a numerically controlled oscillator (NCO

74 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by d

DSP 75Xilinx Blocks• Phase Increment Type: specifies ∆θ to be either constant or register. Choiceof register activates optional ports on the block.• P

76 Xilinx Development SystemXilinx System Generator v2.1 Reference Guidefor k=0, 1, ... , N-1, whereis a principal N-th root of unity.The FFT block ac

DSP 77Xilinx Blocks• Memory Usage:number ofmemorybanks usedtocompute thetransform,one ofSingle, Double, Triple (not used for 16 point FFTs).• Scale Ou

78 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideFigure 3-52: FFT Timing CharacteristicsFor 16-point FFTs, the block is alway

DSP 79Xilinx BlocksThe Dual Port Block Memory LogiCORE datasheet can be found on your local disk at:%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\blkm

8 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideChapter 1IntroductionThis chapter describes the basic concepts and tools of the

80 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by d

Math 81Xilinx Blocks• Polyphase behavior: Decimation, Interpolation, Single rate.• Latency: specify input sample period latency.• Hardware Over-Sampli

82 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by d

Math 83Xilinx Blocks%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\doc\accum.pdfAddSubThe Xilinx AddSub block implements an adder/subtrac

84 Xilinx Development SystemXilinx System Generator v2.1 Reference Guideuses the Xilinx LogiCORE Adder Subtractor V5.0. Otherwise, the block isimpleme

Math 85Xilinx Blockssaturated as needed. A positive value is implemented as an unsigned number, anegative value as signed.• Number of Bits in Constant

86 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by d

Math 87Xilinx BlocksBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model.Figure

88 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideMultThe Xilinx Mult block implements a multiplier. It computes theproduct of t

Math 89Xilinx BlocksFigure 3-60: Mult block parameters dialog box - sequential typeParameters specific to the Mult block are:• Multiplier Type: direc

System Generator 9Introductionconstructs for simulation, its synthesizable subset is far too restrictive for systemdesign.System Generator is a softwa

90 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideNegateThe Xilinx Negate block computes the arithmetic negation (two’scomplemen

Math 91Xilinx Blocks♦ equal-to (a = b)♦ not-equal-to (a != b)♦ less-than (a < b)♦ greater-than (a > b)♦ less-than-or-equal-to (a <= b)♦ great

92 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideScaleThe Xilinx Scale block scales its input by a power of two. The powercan b

Math 93Xilinx BlocksBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by double-clicking the icon in yourSimulink model.Figure

94 Xilinx Development SystemXilinx System Generator v2.1 Reference Guidefundamental sinusoid lie in the half-open interval [-1, 1]. If you need a bal

Math 95Xilinx Blocks64. This corresponds to one CLB per output bit. If the table depth is greater than 64, aquarterwave isstored, andadditional logici

96 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideBlock Parameters Dialog BoxThe block parameters dialog box can be invoked by d

MATLAB I/O 97Xilinx BlocksLogiCOREs, as well as signals and control circuits to drive the clock network.Consequently, most System Generator blocks do

98 Xilinx Development SystemXilinx System Generator v2.1 Reference GuideThe block parameters dialog box can be invoked by double-clicking the icon in

MATLAB I/O 99Xilinx BlocksIt should be noted there is a valid bit that accompanies the data signal. It isconstrained at the same rate. For more infor