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MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide 35
UG257 (v1.1) December 5, 2007 www.xilinx.com
Programming the FPGA, CPLD, or Platform Flash PROM via USB
R
The PROM Formatter then prompts for the name(s) of the FPGA configuration bitstream
file. As shown in Figure 4-18, click OK to start selecting files. Select an FPGA bitstream file
(*.bit). Choose No after selecting the last FPGA file. Finally, click OK to continue.
When PROM formatting is complete, the iMPACT software presents the present settings
by showing the PROM, the select FPGA bitstream(s), and the amount of PROM space
consumed by the bitstream. Figure 4-19 shows an example for a single XC3S500E FPGA
bitstream stored in an XCF04S Platform Flash PROM.
Figure 4-18: Enter FPGA Configuration Bitstream File(s)
UG257_4-18_060906
- MicroBlaze Development 1
- Kit Spartan-3E 1600E 1
- Edition User Guide 1
- Revision History 2
- Table of Contents 3
- Chapter 6: VGA Display Port 4
- Chapter 12: SPI Serial Flash 5
- Chapter 13: DDR SDRAM 6
- Appendix A: Schematics 7
- About This Guide 9
- Additional Resources 10
- Introduction and Overview 11
- Key Components and Features 12
- Design Trade-Offs 13
- UG257_02_01_061306 15
- Push-Button Switches 16
- Rotary Push-Button Switch 17
- Rotary Shaft Encoder 18
- Discrete LEDs 19
- Clock Sources 21
- ±2500 Hz or ±50 ppm 22
- Chapter 3: Clock Sources 24
- FPGA Configuration Options 25
- Spartan-3E 26
- Development Board 26
- Configuration Mode Jumpers 27
- PROG Push Button 28
- DONE Pin LED 28
- Connecting the USB Cable 29
- UG257_04_05_061206 30
- UG257_04_06_0612 30
- UG257 04-07 06906 31
- UG257_04_08_061206 31
- UG257_09_061206 32
- UG257_04_10_061206 33
- UG257_04_11_061206 33
- Generating the PROM File 34
- UG257_04_12_022706 34
- UG257_04_13_061206 34
- UG257_04_14_061206 35
- UG257_04_15_061206 35
- UG257_4-16_061206 36
- UG257_4-17_061206 36
- UG257_4-18_060906 37
- UG257_4-19_061206 38
- UG257_4-20_061206 38
- UG257 4 21 061206 39
- UG257_04_22_061206 39
- UG257_4-23_060106 40
- UG257_4-24_061 40
- UG257_04_25_061206 40
- UG257_04_26_061206 41
- Character LCD Screen 43
- Voltage Compatibility 44
- LCD Controller 46
- UG257_05_04_061206 47
- Command Set 48
- Disabled 49
- Clear Display 49
- Return Cursor Home 49
- Entry Mode Set 49
- Display On/Off 50
- Cursor and Display Shift 50
- Function Set 51
- Set CG RAM Address 51
- Set DD RAM Address 51
- Read Busy Flag and Address 51
- Operation 52
- Power-On Initialization 53
- Display Configuration 53
- VGA Display Port 55
- UG257_06_02_06050 57
- VGA Signal Timing 58
- Chapter 6: VGA Display Port 60
- RS-232 Serial Ports 61
- UG257_07_01_060506 62
- PS/2 Mouse/Keyboard Port 65
- Keyboard 66
- Caps L o c k 67
- Back Space 67
- Mouse Arrow 68
- U257_08_06_060506 69
- Chapter 9 71
- Interface Signals 72
- SPI Communication Details 73
- Communication Protocol 73
- DAC Outputs A and B 74
- Analog Capture Circuit 77
- UG257_10_02_060706 78
- Programmable Pre-Amplifier 79
- SPI Control Interface 80
- Interface 81
- UG257_10_08_061406 83
- Chapter 11 85
- StrataFlash Connections 86
- Shared Connections 89
- SPI Serial Flash 93
- Configuring from SPI Flash 94
- UG257_12_04_061506 95
- UG257_12_05_060806 95
- UG257_12_06_060806 96
- UG257_12_07_060806 96
- UG257_12_08_060806 97
- UG257_12_09_060806 97
- UG257_12_10_060806 98
- UG257_12_11_060806 98
- UG257_12-12_062606 99
- UG257_12_1 99
- 3_060806 99
- UG257_12_14_060806 100
- with Flying Leads 101
- UG257_12_15_060806 101
- NO JUMPER 102
- Additional Design Details 103
- °. The 16-pin SOIC 104
- UG257_12_19_060806 105
- Related Resources 106
- DDR SDRAM 107
- DDR SDRAM Connections 108
- UCF Location Constraints 110
- Chapter 13: DDR SDRAM 112
- Chapter 14 113
- Ethernet PHY Connections 114
- UG257_14_03_060806 115
- Expansion Connectors 117
- Hirose 100-pin Expansion 118
- Connector (J3) 118
- Spartan-3E FPGA 118
- Compatible Board 120
- Mating Receptacle Connectors 120
- Differential I/O 120
- Using Differential Inputs 122
- Using Differential Outputs 123
- Six-Pin Accessory Headers 125
- XC2C64A CoolRunner-II CPLD 129
- FPGA Connections to CPLD 131
- DS2432 1-Wire SHA-1 EEPROM 133
- Appendix A 135
- Schematics 135
- UG257_A01_060606 137
- UG257_A02_060606 139
- Appendix A: Schematics 140
- UG257_A03_060606 141
- Voltage Regulators 142
- Flash, JTAG Connections 144
- UG257_A05_060606 145
- UG257_A06_060606 147
- FPGA I/O Banks 2 and 3 148
- Power Supply Decoupling 150
- UG257_A10_060606 155
- UG257_A11_060606 157
- UG257_A12_060606 159
- Termination 160
- UG257_A13_060606 161
- Appendix B 163
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