Xilinx DS610 Manual de usuario

DS610 July 16, 2007 www.xilinx.com 1Product Specification© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patent

Functional Description10 www.xilinx.com DS610-2 (v2.0) July 16, 2007Product SpecificationRThis page intentionally left blank.

DS610-3 (v2.0) July 16, 2007 www.xilinx.com 11Product Specification© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademar

DC and Switching Characteristics12 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRPower Supply Specifications General Recommended

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 13Product SpecificationRGeneral DC Characteristics for I/O PinsTable 8:

DC and Switching Characteristics14 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRQuiescent Current RequirementsTable 9: Quiescen

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 15Product SpecificationRSingle-Ended I/O StandardsTable 10: Recommended

DC and Switching Characteristics16 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRTable 11: DC Characteristics of User I/Os Using

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 17Product SpecificationRDifferential I/O Standards Figure 3: Differentia

DC and Switching Characteristics18 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationR Figure 4: Differential Output VoltagesTable 13

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 19Product SpecificationRExternal Termination Requirements for Differential

Data Sheet2 www.xilinx.com DS610 July 16, 2007Product SpecificationRThis page intentionally left blank.

DC and Switching Characteristics20 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRSwitching CharacteristicsAll Spartan-3A DSP FPGAs

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 21Product SpecificationRTo create a Xilinx MySupport user account and sign

DC and Switching Characteristics22 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRI/O TimingTable 17: Pin-to-Pin Clock-to-Output

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 23Product SpecificationRTable 18: Pin-to-Pin Setup and Hold Times for th

DC and Switching Characteristics24 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationR Table 19: Setup and Hold Times for the IOB Inp

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 25Product SpecificationRTable 20: Propagation Times for the IOB Input Pa

DC and Switching Characteristics26 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationR Table 21: Input Timing Adjustments by IOSTANDA

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 27Product SpecificationRTable 22: Timing for the IOB Output PathSymbol D

DC and Switching Characteristics28 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRTable 24: Output Timing Adjustments for IOB Con

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 29Product SpecificationRLVC M OS 2 5 Slow 2 mA 5.33 5.33 ns4 mA 2.81 2.81

DS610-1 (v2.0) July 16, 2007 www.xilinx.com 3Product Specification© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademark

DC and Switching Characteristics30 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRDifferential StandardsLVDS_25 1.16 1.16 nsLVDS_33

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 31Product SpecificationRTiming Measurement MethodologyWhen measuring timin

DC and Switching Characteristics32 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRThe capacitive load (CL) is connected between the

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 33Product SpecificationRUsing IBIS Models to Simulate Load Conditions in A

DC and Switching Characteristics34 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRTable 27: Recommended Number of Simultaneously

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 35Product SpecificationRLVCMOS15 Slow 255 55431 31618 188–1512–10Fast 225

DC and Switching Characteristics36 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRConfigurable Logic Block (CLB) TimingTable 28:

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 37Product SpecificationRClock Buffer/Multiplexer Switching Characteristics

DC and Switching Characteristics38 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRBlock RAM TimingTable 32: Block RAM Timing Symb

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 39Product SpecificationRDSP48A TimingTo reference the DSP48A block diagram

Introduction and Ordering Information4 www.xilinx.com DS610-1 (v2.0) July 16, 2007Product SpecificationRArchitectural OverviewThe Spartan-3A DSP fami

DC and Switching Characteristics40 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRTable 34: Clock to Out, Propagation Delays, and

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 41Product SpecificationRDigital Clock Manager (DCM) TimingFor specificatio

DC and Switching Characteristics42 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRTable 36: Switching Characteristics for the DLL

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 43Product SpecificationRDigital Frequency Synthesizer (DFS)Table 37: Rec

DC and Switching Characteristics44 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRPhase Shifter (PS)Miscellaneous DCM TimingTable

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 45Product SpecificationRDNA Port TimingTable 42: DNA_PORT Interface Timi

DC and Switching Characteristics46 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRSuspend Mode TimingFigure 9: Suspend Mode Timing

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 47Product SpecificationRConfiguration and JTAG TimingGeneral Configuration

DC and Switching Characteristics48 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRConfiguration Clock (CCLK) Characteristics Tabl

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 49Product SpecificationRTable 46: Master Mode CCLK Output Frequency by C

Introduction and Ordering InformationDS610-1 (v2.0) July 16, 2007 www.xilinx.com 5Product SpecificationRFigure 1: Spartan-3A DSP Family ArchitectureC

DC and Switching Characteristics50 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRMaster Serial and Slave Serial Mode Timing Figur

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 51Product SpecificationRSlave Parallel Mode Timing Figure 12: Waveforms

DC and Switching Characteristics52 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRSerial Peripheral Interface (SPI) Configuration T

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 53Product SpecificationRTable 52: Configuration Timing Requirements for

DC and Switching Characteristics54 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRByte Peripheral Interface (BPI) Configuration Tim

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 55Product SpecificationRTable 54: Configuration Timing Requirements for

DC and Switching Characteristics56 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRIEEE 1149.1/1553 JTAG Test Access Port TimingFigu

DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 57Product SpecificationRRevision HistoryThe following table shows the revi

DC and Switching Characteristics58 www.xilinx.com DS610-3 (v2.0) July 16, 2007Product SpecificationRThis page intentionally left blank.

DS610-4 (v2.0) July 16, 2007 www.xilinx.com 59Product Specification© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademar

Introduction and Ordering Information6 www.xilinx.com DS610-1 (v2.0) July 16, 2007Product SpecificationRPackage MarkingFigure 2 shows the top marking

Pinout Descriptions60 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationRPackage Pins by TypeEach package has three separate voltage su

Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 www.xilinx.com 61Product SpecificationRPackage Thermal CharacteristicsThe power dissipated by an FPGA

Pinout Descriptions62 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationRCS484: 484-Ball Chip-Scale Ball Grid ArrayThe 484-ball chip-sc

Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 www.xilinx.com 63Product SpecificationR0 IO_L17N_0/GCLK5 F11 GCLK0 IP_0 F12 INPUT0 IO_L13N_0 F13 I/O0

Pinout Descriptions64 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationR1 IO_L03N_1/A1 V20 DUAL1 IP_L08P_1 V22 INPUT1 IO_L03P_1/A0 W19

Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 www.xilinx.com 65Product SpecificationR2 IP_2/VREF_2 Y14 VREF2 IO_L24N_2/D3 Y15 DUAL2 IO_L29N_2 Y16 I/

Pinout Descriptions66 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationR3 IO_L36P_3 V4 I/O3 IO_L35N_3 W1 I/O3 IO_L37N_3 W2 I/O3 IO_L37

Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 www.xilinx.com 67Product SpecificationRGND GND T14 GNDGND GND T15 GNDGND GND T19 GNDGND GND T21 GNDGND

Pinout Descriptions68 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationRUser I/Os by Bank Table 61 and Tabl e 6 2 indicates how the u

Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 www.xilinx.com 69Product SpecificationRCS484 FootprintLeft Half of Package (top view)156I/O: Unrestric

Introduction and Ordering InformationDS610-1 (v2.0) July 16, 2007 www.xilinx.com 7Product SpecificationRRevision HistoryThe following table shows the

Pinout Descriptions70 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationRRight Half of CS484 Package (top view)12 13 14 15 16 17 18 19

Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 www.xilinx.com 71Product SpecificationRFG676: 676-Ball Fine-Pitch Ball Grid ArrayThe 676-ball fine-pit

Pinout Descriptions72 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationR0 IO_L22P_0 D16 I/O0 IO_L21P_0 D17 I/O0 IO_L17P_0 D18 I/O0 IO_

Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 www.xilinx.com 73Product SpecificationR0 VCCO_0 B16 VCCO0 VCCO_0 B22 VCCO1 IO_L01P_1/HDC Y20 DUAL1 IO_

Pinout Descriptions74 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationR1 IO_L50N_1 K21 I/O1 IO_L46N_1 K22 I/O1 IO_L46P_1 K23 I/O1 IP_

Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 www.xilinx.com 75Product SpecificationR2 IO_L46P_2 W17 I/O2 IO_L09P_2 V10 I/O2 IO_L13P_2 V11 I/O2 IO_L

Pinout Descriptions76 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationR2 IO_L41N_2 AC20 I/O2 IO_L45N_2 AC21 I/O2 IO_2 AC22 I/O2 IP_2/

Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 www.xilinx.com 77Product SpecificationR3 IO_L48P_3 T10 I/O3 IO_L36P_3/VREF_3 R1 VREF3 IO_L36N_3 R2 I/O

Pinout Descriptions78 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationR3 IP_L04P_3 C2 INPUT3 IO_L02N_3 B1 I/O3 IO_L02P_3 B2 I/O3 IP_L

Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 www.xilinx.com 79Product SpecificationRGND GND F21 GNDGND GND F26 GNDGND GND C3 GNDGND GND C9 GNDGND G

Introduction and Ordering Information8 www.xilinx.com DS610-1 (v2.0) July 16, 2007Product SpecificationRThis page intentionally left blank.

Pinout Descriptions80 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationRUser I/Os by Bank Table 64 indicates how the available user-I/

Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 www.xilinx.com 81Product SpecificationRFG676 Footprint - XC3SD1800A FPGALeft Half of Package (top view

Pinout Descriptions82 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationRRight Half of FG676 Package (top view)14 15 16 17 18 19 20 21

Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 www.xilinx.com 83Product SpecificationRXC3SD3400A FPGATabl e 6 5 lists all the FG676 package pins fo

Pinout Descriptions84 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationR0 IO_L05P_0 D22 I/O0 IO_L06P_0 D23 I/O0 IO_L44P_0 C5 I/O0 IO_L

Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 www.xilinx.com 85Product SpecificationR1 IO_L12N_1 U18 I/O1 IO_L12P_1 U19 I/O1 IO_L10N_1 U20 I/O1 IO_L

Pinout Descriptions86 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationR1 IP_1/VREF_1 G25 VREF1 IO_L58P_1/VREF_1 F22 VREF1 IO_L56N_1 F

Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 www.xilinx.com 87Product SpecificationR2 IO_L48P_2 AF23 I/O2 IO_L52P_2/D0/DIN/MISO AF24 DUAL2 IO_L51P_

Pinout Descriptions88 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationR2 VCCO_2 AB8 VCCO2 VCCO_2 AB14 VCCO2 VCCO_2 AB19 VCCO3 IO_L53P

Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 www.xilinx.com 89Product SpecificationR3 IO_L23N_3 K2 I/O3 IO_L23P_3 K3 I/O3 IO_L22N_3 K4 I/O3 IO_L22P

DS610-2 (v2.0) July 16, 2007 www.xilinx.com 9Product Specification© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademark

Pinout Descriptions90 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationRGND GND P12 GNDGND GND P16 GNDGND GND P19 GNDGND GND P24 GNDGN

Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 www.xilinx.com 91Product SpecificationRGND GND A23 GNDGND GND A26 GNDVCCAUX DONE AB21 CONFIGVCCAUX PRO

Pinout Descriptions92 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationRUser I/Os by Bank Table 66 indicates how the available user-I/

Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 www.xilinx.com 93Product SpecificationRFG676 Footprint - XC3SD3400A FPGALeft Half of Package (top view

Pinout Descriptions94 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationRRight Half of FG676 Package (top view)14 15 16 17 18 19 20 21

Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 www.xilinx.com 95Product SpecificationRFootprint Migration DifferencesThere are multiple migration foo

Pinout Descriptions96 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationRMigration RecommendationsThere are multiple pinout differences

Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 www.xilinx.com 97Product SpecificationRRevision HistoryThe following table shows the revision history

Pinout Descriptions98 www.xilinx.com DS610-4 (v2.0) July 16, 2007Product SpecificationRThis page intentionally left blank.