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ML310 User Guide www.xilinx.com 51

UG068 (v1.01) August 25, 2004 1-800-255-7778

Board Hardware

Table 2-14 shows a block diagram of the FPGA in relation to the SMBus accelerator and the

IIC bus.

Note:

Either the XC2VP30 or the ALi M1535D+ can master the IIC bus but not simultaneously

Figure 2-14: SMBus and IIC Block Diagram

U37

Virtex-II Pro

FPGA

XC2VP30

U15

ALi

Southbridge

M1535 D+

U27

SMBUS

Accelerator

ADDR:

0x5C

ADDR:

0xA2

RTClock

ADDR:

0xA0

EEPROM

SPD

EEPROM

Voltage

Temp

Monitor

LTC1694

Temperature

U20

LM87

VCC12V_P

VCC5V

VCC2V5

VVCC3_PCI

VCC1V5

IIC Bus

PCI Bus

U22

RTC8566

U21

24LC64

Note: Located on

DDR DIMM P7

1 2 ... 46 47 48 49 50 51 52 53 54 55 56 ... 69 70

ML310 User 1
1-800-255-7778 2
ML310 User Guide 3
UG068 (v1.01) August 25, 2004 3
Table of Contents 5
About This Manual 7
Conventions 8
Online Document 9
Chapter : 10
Introduction 11
PowerPC™ 405 Core 12
Virtex-II FPGA Fabric 13
Foundation ISE 14
Synthesis 15
Embedded Development Kit 16
Platform 17
ML310 Embedded Development 17
Figure 2-1: ML310 Board 18
Features 19
Board Hardware 20
DDR Memory 21
DDR Signaling 22
DDR Memory Expansion 22
Serial Port FPGA UART 26
System ACE CF Controller 27
Non-Volatile Storage 28
XC2VP30 Connectivity 28
JTAG Connection to XC2VP30 29
GPIO LEDs and LCD 30
GPIO LED Interface 32
GPIO LCD Interface 32
CPU Debug and CPU Trace 33
GND, G1, G2, G3, G4, G5 34
MICTOR 38 34
CPU Debug Connector Pinout 35
USB, connector assembly J3 43
IDE, connectors J15 and J16 44
GPIO, connector J5 45
System Management Bus (SMBus) 45
AC97 Audio 46
Flash ROM, U4 47
IIC/SMBus Interface 49
IIC bus 51
FPGA PCI interface 52
SPI Addressing 53
Push Buttons 53
CPU Reset, SW2 54
High-Speed I/O 61
ML310 PM Connectors 62
PM1 Connector 63
PM2 Connector 63
ML310 PM Utility Pins 64
ML310 PM User I/O Pins 65
FPGA Bank 66
ML310 PM2 User I/O 68

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Xilinx ML310 Manual de usuario Pagina 51

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