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ML310 User Guide www.xilinx.com 21
UG068 (v1.01) August 25, 2004 1-800-255-7778
Board Hardware
R
II Pro FPGA I/O can be configured to use different IO standards such as SSTL2 as required
on the DDR DIMM interface. Please review the ML310 Virtex-II Pro data sheet for more
information regarding I/O standards.
Figure 2-3 shows the top-level clocking for the ML310 board.
DDR Memory
DDR DIMM
The ML310 includes a registered 256MB PC3200 Double Data Rate (DDR) Dual Inline
Memory Module (DIMM) with an industry standard 184-pin count. The DDR DIMM is
commercially available from Wintec Industries as part number W4F232726HA-5Q. The
associated datasheet is provided on the ML310 CDROM. The DDR DIMM is
manufactured using nine Infineon HYB25D256800BT-5, 32Mx8 DDR SDRAM devices with
13-row address lines, 10-column address lines, and 4 bank select lines. Read and write
access to the Infineon devices is programmable in burst lengths of 2, 4, or 8 column
locations. The memory module inputs and outputs are compatible with SSTL2 signaling.
Serial Presence Detect (SPD) using an SMBus interface to the DDR DIMM is also
supported. Please refer to section “IIC/SMBus Interface” for more details on accessing the
DIMM module’s SPD EEPROM.
Figure 2-3: Top-Level Clocking
PM IO
2.5V
LVDS
DDR
DIMM
64 bit
256MB
PM IO
2.5V
LVDS
PCI
BUS
3.0V
DCM
X0Y0
DCM
X1Y0
DCM
X2Y0
DCM
X3Y0
DCM
X0Y1
DCM
X1Y1
DCM
X2Y1
DCM
X03Y1
7S 6P 5S 4P 3S 2P 1S 0P
7P 6S 5P 4S 3P 2S 1P 0S
BANK 0
2.5V
BANK 1
3.0V
BANK 2
3.0V
BANK 3
2.5V
BANK 4
2.5V
BANK 5
2.5V
BANK 6
2.5V
BANK 7
2.5V
LVDS_CLK_LOC_N
LVDS_CLK_LOC_P
USER_CLKSYS
(not used)
DDR_CLK_FB
SYACE_FPGA_CLK
PM_CLK_BOT
LVDS_CLK_EXT_N
LVDS_CLK_EXT_P
LVDS_CLK_LOC_N
LVDS_CLK_LOC_P
LVDS_CLK_EXT_N
LVDS_CLK_EXT_P
PM_CLK_TOP
USER_SMA_CLK
SYS_CLK
(user_clk_pci)
LEDsLCDSYSACE IIC UART
PM IO
3V
CPU
DEBUG
SPITRACE
PM IO
2.5V
12
(6 LVDS)
72
(36 LVDS)
PCI_P_CLK1
thru
PCI_P_CLK4
PCI_P_CLK5
DDR_CLK
DDR_CLKB
DDR_CLK_FB
Note:
All 3 DDR
Clock nets
are length
matched
Note:
All 5 PCI
Clock nets
are length
matched
26
SYACE_FPGA_CLK
OSC
33MHz
J17
X8
OSC
156.25
MHz
OSC
125MHz
J21
J20
X7
X9
PM1
8
MGTs
(to FPGA)
PM2
OSC
100MHz
X10
6
(3 LVDS)
OSC
X6
- ML310 User 1
- 1-800-255-7778 2
- ML310 User Guide 3
- UG068 (v1.01) August 25, 2004 3
- Table of Contents 5
- About This Manual 7
- Conventions 8
- Online Document 9
- Chapter : 10
- Introduction 11
- PowerPC™ 405 Core 12
- Virtex-II FPGA Fabric 13
- Foundation ISE 14
- Synthesis 15
- Embedded Development Kit 16
- Platform 17
- ML310 Embedded Development 17
- Figure 2-1: ML310 Board 18
- Features 19
- Board Hardware 20
- DDR Memory 21
- DDR Signaling 22
- DDR Memory Expansion 22
- Serial Port FPGA UART 26
- System ACE CF Controller 27
- Non-Volatile Storage 28
- XC2VP30 Connectivity 28
- JTAG Connection to XC2VP30 29
- GPIO LEDs and LCD 30
- GPIO LED Interface 32
- GPIO LCD Interface 32
- CPU Debug and CPU Trace 33
- GND, G1, G2, G3, G4, G5 34
- MICTOR 38 34
- CPU Debug Connector Pinout 35
- USB, connector assembly J3 43
- IDE, connectors J15 and J16 44
- GPIO, connector J5 45
- System Management Bus (SMBus) 45
- AC97 Audio 46
- Flash ROM, U4 47
- IIC/SMBus Interface 49
- IIC bus 51
- FPGA PCI interface 52
- SPI Addressing 53
- Push Buttons 53
- CPU Reset, SW2 54
- High-Speed I/O 61
- ML310 PM Connectors 62
- PM1 Connector 63
- PM2 Connector 63
- ML310 PM Utility Pins 64
- ML310 PM User I/O Pins 65
- FPGA Bank 66
- ML310 PM2 User I/O 68
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