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UG199 (v1.2.1) June 15, 2009
Hardware Schematic Diagram
R
Array Connector Numbering
Figure C-12 shows the LCD connections for Bank 0.
Figure C-12: LCD Connections (Bank 0)
Bank 0
Connector Pin
ABCDE FGH I
D9 LCD_D0
10
D7 LCD_D4
9
D5 LCD_D5
8
D3 LCD_D6
7
D1 LCD_D7
6
E10 LCD_RST
5
E8 LCD_D1
4
E6 LCD_D2
3
E4 LCD_D3
2
E2 LCD_ENA
1
F5 LCD_R/W
F3 LCD_RSEL
Connector J32
F1 LCD_CS1B
UG199_C_12_050106
- Virtex-5 FPGA ML561 1
- Memory Interfaces 1
- Development Board 1
- Revision History 2
- Table of Contents 3
- Chapter 6: Configuration 4
- Appendix A: FPGA Pinouts 4
- Appendix C: LCD Interface 5
- About This Guide 7
- Additional Support Resources 8
- Conventions 9
- Terminology 9
- Preface: About This Guide 10
- Introduction 11
- Chapter 1: Introduction 14
- Getting Started 15
- Applying Power to the Board 16
- Hardware Description 17
- DDR400 SDRAM Components 19
- DDR2 DIMM 19
- DDR2 SDRAM Components 20
- QDRII SRAM 20
- RLDRAM II Devices 20
- Memory Details 21
- DDR2 SDRAM DIMM 23
- QDRII and RLDRAM II Memories 25
- External Interfaces 27
- 200 MHz LVPECL Clock 28
- SMA Clock 28
- 33 MHz Clock 28
- GTP Clocks 29
- General-Purpose Headers 29
- DIP Switch 29
- Seven-Segment Displays 30
- Light Emitting Diodes (LEDs) 30
- Pushbuttons 30
- Power On or Off Slide Switch 31
- Soft Touch Probe Points 31
- Power Measurement Header 31
- Power Regulation 33
- Voltage Regulators 34
- Board Design Considerations 36
- Electrical Requirements 39
- Power Consumption 41
- FPGA Internal Power Budget 46
- Chapter 5 47
- Configuration 51
- 1. X = Supported 52
- 2. — = Not applicable 52
- System ACE Interface 53
- Chapter 6: Configuration 54
- ML561 Hardware-Simulation 55
- Correlation 55
- Test Setup 56
- UG199_c7_01_062707 57
- Table 7-3: DIP[1:2] Settings 60
- Voltage (mV) 61
- Time (ps) 61
- (DDR2 Memory Via) 62
- Time (ns) 63
- DDR2 Component Read Operation 65
- Cursor 1: 697.1 mV, 1.2345 ns 66
- Cursor 2: 774.6 mV, 2.5191 ns 66
- UG199_c7_21_071907 70
- UG199_c7_30_071907 76
- QDRII Write Operation 81
- QDRII Read Operation 86
- Summary and Recommendations 91
- FPGA Pinouts 95
- FPGA #1 Pinout 97
- FPGA #2 Pinout 100
- Appendix A: FPGA Pinouts 102
- FPGA #3 Pinout 108
- Bill of Materials 115
- Appendix B: Bill of Materials 116
- UG199 (v1.2.1) June 15, 2009 117
- LCD Interface 119
- Hardware Schematic Diagram 120
- Peripheral Device KS0713 121
- Controller 122
- LCD Panel 122
- LED Backlight 122
- 128 x 64 DOTS 122
- Controller – Operation 123
- Appendix C: LCD Interface 124
- UG199_C_05_050106 126
- ♦ The LCD bias is set to: 129
- Instruction Set 130
- Design Examples 134
- Display Command Byte 135
- UG199_C_09_050106 136
- Array Connector Numbering 139
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