Xilinx Virtex-5 FPGA ML561 Manual de usuario Pagina 128
- Pagina / 140
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
128 www.xilinx.com Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
Appendix C: LCD Interface
R
• The voltage follower and voltage regulator are set to:
♦ Five times boost mode
♦ The V4, V3, V2, V1, and V0 outputs depend on the bias settings of 1/9 or 1/7.
Because of these default settings, the following display controller connections are not used:
• DISP: Turns into an output when Master mode is selected
• FRS: Static driver segment output
• M: Used in Master/Slave display configurations
• CL: Clock pin used in Master/Slave display configurations
When RESETB is Low, the display controller is initialized as indicated in Table C-3.
When RESETB is High, the display must be initialized. The first steps to be taken to
guarantee correct operation of the display and the controller are:
• Configure the ADC bit. This bit determines the scanning direction of the segments.
♦ When the RESETB signal is active, ADC is reset to 0, meaning that the segments
are scanned from SEG1 up to SEG132.
♦ When ADC is set to 1, the segments are scanned in opposite direction.
• Configure the SHL bit. This bit sets the scanning direction of the COM lines.
♦ When the RESETB signal is active, SHL is reset to 0, meaning that the segments
are scanned from COM1 up to COM64.
♦ When SHL is set to 1, the common lines are scanned in opposite direction.
Tab l e C -3 : Display Controller Initialization (RESETB is Low)
Parameter Initial Value
Display OFF
Entire Display OFF
ADC Select OFF
Reverse Display OFF
Power Control 0,0,0 (VC, VR, VF)
LCD Bias 1/7
Read-Modify-Write OFF
SHL Select OFF
Static Indicator Mode OFF
Static Indicator Register 0,0 (S1, S0)
Display Start 0 (First line)
Column Address 0
Page Address 0
Regulator Select 0,0,0 (R2, R1, R0)
Reference Voltage OFF
Reference Voltage Register 1,0,0,0,0,0 (SV5, SV4, SV3, SV2, SV1, SV0)
- Virtex-5 FPGA ML561 1
- Memory Interfaces 1
- Development Board 1
- Revision History 2
- Table of Contents 3
- Chapter 6: Configuration 4
- Appendix A: FPGA Pinouts 4
- Appendix C: LCD Interface 5
- About This Guide 7
- Additional Support Resources 8
- Conventions 9
- Terminology 9
- Preface: About This Guide 10
- Introduction 11
- Chapter 1: Introduction 14
- Getting Started 15
- Applying Power to the Board 16
- Hardware Description 17
- DDR400 SDRAM Components 19
- DDR2 DIMM 19
- DDR2 SDRAM Components 20
- QDRII SRAM 20
- RLDRAM II Devices 20
- Memory Details 21
- DDR2 SDRAM DIMM 23
- QDRII and RLDRAM II Memories 25
- External Interfaces 27
- 200 MHz LVPECL Clock 28
- SMA Clock 28
- 33 MHz Clock 28
- GTP Clocks 29
- General-Purpose Headers 29
- DIP Switch 29
- Seven-Segment Displays 30
- Light Emitting Diodes (LEDs) 30
- Pushbuttons 30
- Power On or Off Slide Switch 31
- Soft Touch Probe Points 31
- Power Measurement Header 31
- Power Regulation 33
- Voltage Regulators 34
- Board Design Considerations 36
- Electrical Requirements 39
- Power Consumption 41
- FPGA Internal Power Budget 46
- Chapter 5 47
- Configuration 51
- 1. X = Supported 52
- 2. — = Not applicable 52
- System ACE Interface 53
- Chapter 6: Configuration 54
- ML561 Hardware-Simulation 55
- Correlation 55
- Test Setup 56
- UG199_c7_01_062707 57
- Table 7-3: DIP[1:2] Settings 60
- Voltage (mV) 61
- Time (ps) 61
- (DDR2 Memory Via) 62
- Time (ns) 63
- DDR2 Component Read Operation 65
- Cursor 1: 697.1 mV, 1.2345 ns 66
- Cursor 2: 774.6 mV, 2.5191 ns 66
- UG199_c7_21_071907 70
- UG199_c7_30_071907 76
- QDRII Write Operation 81
- QDRII Read Operation 86
- Summary and Recommendations 91
- FPGA Pinouts 95
- FPGA #1 Pinout 97
- FPGA #2 Pinout 100
- Appendix A: FPGA Pinouts 102
- FPGA #3 Pinout 108
- Bill of Materials 115
- Appendix B: Bill of Materials 116
- UG199 (v1.2.1) June 15, 2009 117
- LCD Interface 119
- Hardware Schematic Diagram 120
- Peripheral Device KS0713 121
- Controller 122
- LCD Panel 122
- LED Backlight 122
- 128 x 64 DOTS 122
- Controller – Operation 123
- Appendix C: LCD Interface 124
- UG199_C_05_050106 126
- ♦ The LCD bias is set to: 129
- Instruction Set 130
- Design Examples 134
- Display Command Byte 135
- UG199_C_09_050106 136
- Array Connector Numbering 139
© 2020, manymanuals.es. Todos los derechos reservados | 0.037 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentarios a estos manuales