Xilinx UG018 manuales

Xilinx UG018 Manual de usuario (236 paginas)

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Tabla de contenidos

PowerPC™ 405 Processor

1

Block Reference Guide

1

1-800-255-7778

2

UG018 (v2.0) August 20, 2004

3

Table of Contents

5

Guide Contents

9

Additional Resources

10

Conventions

10

Online Document

11

Registers

12

Register Descriptive Name

13

Preface: About This Guide

14

PowerPC Architecture

17

Virtual Environment

19

Operating Environment

19

PowerPC 405 Software Features

21

Privilege Modes

22

Address Translation Modes

22

Addressing Modes

23

Data Types

23

Register Set Summary

23

General-Purpose Registers

24

Special-Purpose Registers

25

Machine-State Register

25

Condition Register

25

Device Control Registers

25

Central-Processing Unit

26

Exception Handling Logic

27

Memory Management Unit

27

Instruction and Data Caches

28

Timer Resources

29

PowerPC 405 Interfaces

29

PowerPC 405 Performance

30

Input/Output Interfaces

33

Signal Naming Conventions

34

UG018_02_01_051204

36

C405CPMTIMERIRQ (Output)

39

C405CPMTIMERRESETREQ (Output)

39

C405CPMCORESLEEPREQ (Output)

39

Virtex-4 Specific

40

CPU Control Interface

41

TIEC405MMUEN (Input)

42

TIEC405DISOPERANDFWD (Input)

42

Reset Interface

43

UG018_03_102001

44

C405RSTCORERESETREQ (Output)

45

C405RSTCHIPRESETREQ (Output)

45

C405RSTSYSRESETREQ (Output)

45

RSTC405RESETCORE (Input)

46

RSTC405RESETCHIP (Input)

46

RSTC405RESETSYS (Input)

46

JTGC405TRSTNEG (Input)

47

Guarded Storage

50

C405PLBICUREQUEST (Output)

52

C405PLBICUABUS[0:29] (Output)

52

C405PLBICUSIZE[2:3] (Output)

53

C405PLBICUCACHEABLE (Output)

53

C405PLBICUU0ATTR (Output)

54

C405PLBICUABORT (Output)

54

PLBC405ICUADDRACK (Input)

55

PLBC405ICUSSIZE1 (Input)

55

PLBC405ICURDDACK (Input)

56

UG018_10_102001

57

PLBC405ICUBUSY (Input)

58

PLBC405ICUERR (Input)

59

Abbreviation

61

Description Where Used

61

PLB/BIU Outputs:

62

ISPLB Aborted Fetch Request

67

Data-Side PLB Operation

68

Address Pipelining

71

Unaligned Accesses

71

UG018_05_102001

72

C405PLBDCUREQUEST (Output)

73

C405PLBDCURNW (Output)

74

C405PLBDCUABUS[0:31] (Output)

74

C405PLBDCUSIZE2 (Output)

74

C405PLBDCUCACHEABLE (Output)

75

C405PLBDCUWRITETHRU (Output)

75

C405PLBDCUU0ATTR (Output)

76

C405PLBDCUGUARDED (Output)

76

C405PLBDCUBE[0:7] (Output)

76

Byte Enables [0:7]

77

C405PLBDCUABORT (Output)

78

PLBC405DCUADDRACK (Input)

80

PLBC405DCUSSIZE1 (Input)

81

PLBC405DCURDDACK (Input)

82

PLBC405DCUWRDACK (Input)

83

PLBC405DCUBUSY (Input)

84

PLBC405DCUERR (Input)

84

Table 2-20

100

External DCR Bus Interface

101

UG018_52_042304

102

UG018_53_051204

103

DCR Slave

103

Processor Core

103

Virtex-4-FX

104

DCRC405ACK/EXTDCRACK (Input)

106

PPC405 Outputs:

107

DCR Outputs:

107

UG018_07_102001

110

EICC405CRITINPUTIRQ

110

EICC405EXTINPUTIRQ

110

PPC405 JTAG Debug Port

111

JTAG Instruction Register

113

UG018_70_100803

114

UG018_71_100803

114

UG018_76_032504

115

UG018_75_032504

116

PPC405 Cores)

117

UG018_73_032504

118

JTAG Logic

119

Primitive

120

Debug Interface

128

DBGC405EXTBUSHOLDACK (Input)

129

DBGC405DEBUGHALT (Input)

129

C405DBGWBFULL (Output)

130

C405DBGWBIAR[0:29] (Output)

130

C405DBGWBCOMPLETE (Output)

130

C405DBGMSRWE (Output)

130

Trace Interface

131

C405TRCCYCLE (Output)

133

TRCC405TRIGGEREVENTIN (Input)

134

TRCC405TRACEDISABLE (Input)

134

If Unused Function

135

MCBCPUCLKEN (Input)

136

MCBJTAGEN (Input)

136

MCBTIMEREN (Input)

137

MCPPCRST (Input)

137

Introduction

139

Functional Features

140

OCM Controller Operation

142

Execution Re-ordering

144

Store-data Bypass

144

UG018_37b_12080

145

UG018_37_020102

145

DSOCM Input Ports

146

DSOCM Input Ports: Attributes

147

DSOCM Output Ports

148

DSOCM-to-BRAM Interfaces

149

*ENA can be tied off

150

To/from FPGA logic

151

(application-specific use

151

Global signals from FPGA

151

UG018_37c_042304

152

UG018_38_020102

152

UG018_38b_11210

153

ISOCM Input Ports, Attributes

154

ISOCM Output Ports

155

UG018_49_112103

157

Programmer’s Model

158

DSCNTL Registers

159

ISCNTL Registers

160

UG018_46_042304

162

UG018_46b_042304

163

UG018_47_04230

164

UG018_47b_05120

165

DCR Write Access

166

DCR Read Access

167

UG018_69_042304

168

UG018_69b_05120

169

Single-Cycle Mode

170

Multi-Cycle Mode

170

ISOCM Instruction Fetching

170

UG018_60_03060

171

Writing to ISBRAM

172

UG018_66_03060

173

UG018_67_030603

174

UG018_62_03060

175

DSOCM Store, Fixed Latency

176

Controller Only)

177

UG018_62c_11210

178

UG018_63c_112103

179

UG018_64c_12080

180

UG018_65c_12080

180

References

181

FCM Instruction Processing

184

UG018_04_01_040904

184

Resynchronization_Interface

184

Instruction Classes

185

Enabling the APU Controller

185

Instruction Format

186

Instruction Decoding

187

FCM Load/Store Instructions

188

Integer Divide Instructions

189

FCM Exceptions

190

FCM Instruction Flushing

190

Execution Hazards

190

APU Controller Configuration

191

UDI Configuration Registers

192

Interface Definition

193

APU Controller Input Signals

194

APU Controller Output Signals

196

APU Controller Attributes

197

APU Controller

198

Configuration Field

198

TIEAPUCONTROL Bits

198

Autonomous Transactions

199

UG018_04_03_032504

200

Blocking Transactions

201

Non-Blocking Transactions

202

FCM Load Instruction

203

FCM Store Instruction

204

FCM Exception

205

UG018_04_11_032504

206

UG018_04_12_042304

206

Appendix A

207

RISCTrace Interface

209

Signal Summary

213

Appendix B: Signal Summary

214

Processor Block Timing Model

223

Parameter Function Signals

225

UG012_C1_02_121701

232

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