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132 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 9: Configuration and Status
R
1.10 100BASE-T2 Full
Duplex
Always returns a ‘0’ for this bit since
100BASE-T2 Full Duplex is not supported
returns 0 0
1.9 100BASE-T2 Half
Duplex
Always returns a ‘0’ for this bit since
100BASE-T2 Half Duplex is not supported
returns 0 0
1.8 Extended Status Always returns a ‘1’ for this bit to indicate
the presence of the Extended Register
(Register 15)
returns 1 1
1.7 Unidirectional Ability Always returns 1, writes ignored returns 1 1
1.6 MF Preamble
Suppression
Always returns a ‘1’ for this bit to indicate
that Management Frame Preamble
Suppression is supported
returns 1 1
1.5 Auto- Negotiation
Complete
Ignore this bit because Auto-Negotiation
is not included.
returns 1 1
1.4 Remote Fault Always returns a ‘0’ for this bit because
Auto-Negotiation is not included.
returns 0 0
1.3 Auto- Negotiation
Ability
Ignore this bit because Auto-Negotiation
is not included.
returns 0 0
1.2 Link Status
1
1 = Link is up
0 = Link is down
Latches '0' if Link Status goes down.
Clears to current Link Status on read.
See table note for Link Status behavior.
read only
self
clearing
on read
0
1.1 Jabber Detect Always returns a ‘0’ for this bit since
Jabber Detect is not supported
returns 0 0
1.0 Extended Capability Always returns a ‘0’ for this bit since no
extended register set is supported
returns 0 0
1. When high, the link is valid: synchronization of the link has been obtained and Auto-Negotiation (if present and enabled) has
completed.
When low, a valid link has not been established. Either link synchronization has failed or Auto-Negotiation (if present and
enabled) has failed to complete.
Regardless of whether Auto-Negotiation is enabled or disabled, there can be some delay to the deassertion of this signal
following the loss of synchronization of a previously successful link. This is due to the Auto-Negotiation state machine which
requires that synchronization is lost for an entire link timer duration before changing state. For more information, see the 802.3
specification.
Table 9-15: Status Register (Register 1) (Continued)
Bit(s) Name Description Attributes
Default
Value
- LogiCORE™ IP 1
- Ethernet 1000BASE-X 1
- PCS/PMA or SGMII v9.1 1
- Revision History 2
- Table of Contents 3
- Chapter 10: Auto-Negotiation 5
- Appendix B: Core Latency 7
- Appendix F: Debugging Guide 7
- Schedule of Figures 9
- Schedule of Tables 13
- About This Guide 15
- Conventions 16
- Online Document 17
- Preface: About This Guide 18
- IP core 19
- Additional Core Resources 20
- Technical Support 20
- Feedback 20
- Document 21
- Chapter 1: Introduction 22
- Core Architecture 23
- GMII Block 24
- PCS Transmit Engine 24
- RocketIO Interface Block 25
- 8B/10B Decoder 26
- Receiver Elastic Buffer 26
- TBI Block 26
- 8B/10B Encoder 26
- Core Interfaces 27
- Chapter 2: Core Architecture 28
- Client Side Interface 31
- Common Signal Pinout 33
- Signal Direction Description 35
- Physical Side Interface 36
- Chapter 3 39
- Select Standard 40
- Core Functionality 40
- Physical Interface 41
- MDIO Management Interface 41
- RocketIO Tile Configuration 43
- Output Generation 44
- Designing with the Core 45
- Design Guidelines 50
- Write an HDL Application 51
- Synthesize your Design 51
- Create a Bitstream 51
- Know the Degree of Difficulty 51
- Keep it Registered 52
- Use Supported Design Flows 52
- Chapter 5 53
- GMII Reception 54
- Frame Reception with Errors 55
- False Carrier 56
- Bit[0]: Link Status 56
- Bit[1]: Link Synchronization 56
- GMII Transmission 57
- Overview 59
- Implementing External GMII 61
- GMII Receiver Logic 66
- The Ten-Bit Interface 69
- Receiver Logic 70
- Ten-Bit-Interface Logic 71
- Method 2 74
- Block Level 77
- 1000BASE-X with RocketIO 79
- (Block Level from 84
- Transceivers for 1000BASE-X 91
- Chapter 8 95
- Analysis 96
- Closely Related Clock Sources 98
- UG155 March 24, 2008 100
- '0' 102
- '1' 102
- Virtex-5 RocketIO GTP Wizard 103
- REFCLKOUT 104
- Virtex-5 RocketIO GTX Wizard 105
- Virtex-II Pro Devices 107
- Virtex-4 FX Devices 109
- Virtex-5 LXT and SXT Devices 111
- Virtex-5 FXT Devices 113
- Configuration and Status 115
- MDIO Transactions 116
- MDIO Addressing 117
- Register Address (REGAD) 118
- Management Registers 119
- Register 0: Control Register 120
- Register 1: Status Register 122
- Register 8: Next Page Receive 127
- Register 15: Extended Status 128
- Register 0: SGMII Control 135
- Register 1: SGMII Status 137
- Optional Configuration Vector 151
- Auto-Negotiation 153
- SGMII Standard 155
- 1000BASE-X Standard 156
- Simulating Auto-Negotiation 156
- SGMII Standards 157
- Operation of the Core 158
- Constraining the Core 161
- Clock Period Constraints 162
- Setting MGT Attributes 162
- Constraints 163
- MGT Placement Constraints 165
- Switching Constraints 168
- Ten-Bit Interface Constraints 168
- TBI Input Setup/Hold Timing 170
- Virtex-4 Devices 171
- GMII IOB Constraints 173
- GMII Input Setup/Hold Timing 174
- Virtex-4 devices 175
- Virtex-5 devices 175
- Virtex-4 or Virtex-5 Devices 176
- = 8 - 6.501 177
- = 1.499 ns 177
- = 7.893 - 8 177
- = -0.107 ns 177
- Interfacing to Other Cores 179
- Switching) Functionality 185
- IOB LOGIC 187
- Special Design Considerations 197
- Loopback 199
- Transceivers 199
- Implementing the Design 201
- Implementation 202
- Static Timing Analysis 203
- Generating a Bitstream 203
- Generating a Simulation Model 203
- Using the Model 203
- Virtex-5 Devices 204
- Interoperability 205
- Transmit Path Latency 207
- Receive Path Latency 207
- Appendix C 209
- 1000BASE-X State Machines 211
- Start of Frame Encoding 212
- Reception of the Even Case 213
- The Odd Transmission Case 213
- Reception of the Odd Case 214
- End of Frame Encoding 215
- Appendix E 219
- 5000 x 18 = 90000 bytes 220
- Virtex-4 FX 221
- 122 - Overflow Mark 222
- 6 - Underflow Mark 222
- Rx Elastic Buffer 223
- Clock Correction 224
- Jumbo Frame Reception 226
- Debugging Guide 227
- RocketIO Transceiver Specific 229
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